Four lab exercises for the Analog Integrated Circuit Design course at the University of Padova (Prof. Andrea Neviani), each following the same discipline: size the circuit by hand with the long-channel model first, then simulate it in Cadence Virtuoso, and explain the gap when the two disagree. In order: characterizing CMOS current mirrors and designing a wide-swing cascode; sizing a fully-differential current-mirror OTA to a gain, bandwidth and offset spec; building a capacitive-feedback amplifier around a separate two-stage OTA and compensating it until it settles; and tuning a low-voltage band-gap reference until it stops drifting with temperature. All four are summarized below, with the full calculations, plots and Monte-Carlo analysis in the linked report.
Lab 01
Where a current mirror stops mirroring
In a basic n-type mirror the identity IOUT = N·IIN holds at exactly one output voltage: the point where the output device sees the same VDS as the diode-connected input device, so the channel-length-modulation factor is identical on both sides and cancels in the ratio. Everywhere else it does not — the output current drifts while that device stays saturated, then collapses once it falls into triode. Two geometry variants make the same point: a shorter output device overshoots the ratio (DIBL lowers its threshold), narrower fingers undershoot it (the narrow-width effect raises it). Corner runs (TYP, SS at −20 °C, FF at 85 °C) and a 100-run Monte Carlo then quantify the spread: hand calculation predicts a 7.95 μA standard deviation on the output current error against 5.01 μA simulated — same order, but pessimistic — and the histogram sits centred on −12.9 μA rather than zero, because global process spread moves both transistors together while mismatch only widens the distribution.
The follow-up is a wide-swing cascode mirror with a spec of its own: 500 μA out of a 100 μA reference, at least 100 kΩ of output resistance, and an output still usable down to 0.4 V. Sizing the bias device until all four cascode transistors sit at roughly 0.25 V of VDS — the edge of saturation, with equal headroom — gives 135 kΩ and a mirroring error of 3.9 μA, 0.78%, at the edge of that swing.
Lab 02
Sizing an OTA to a hard spec
The starting sizing of a fully-differential current-mirror OTA — p-type input pair, n-type mirror load, ideal common-mode feedback, 1 pF at each output — misses all three specifications at once: 14.2 dB of gain against 30 dB, a 54 MHz unity-gain frequency against 1 GHz, and 4.92 mV of offset against 4 mV. Gain and bandwidth are set by nearly independent quantities — the mirror ratio and the tail current fix the transconductance and with it the GBW, the length of the output devices fixes the resistance at that node and with it the gain — so raising the mirror ratio to 7.5, the tail multiplier to 6 and stretching the output devices to 1 μm closes both gaps at once, while widening the input pair from 7.6 to 44 μm pulls the offset back under spec. The measured GBW lands at 1.05 GHz rather than the ~3 GHz the ideal expression promises, because those wide output devices add roughly 1.8 pF of their own parasitic capacitance on top of the 1 pF load.
Lab 03
From 25° of phase margin to a clean 20 ns settle
Close a fully-differential two-stage OTA — a different amplifier from Lab 02 — inside a capacitive-feedback loop, and the sizing you start from is barely usable: two high-impedance internal nodes put two poles close together, the topology adds a right-half-plane zero, and what is left is 37.4 dB of loop gain with about 25° of phase margin. The closed-loop response peaks by 13 dB near 200 MHz, and every edge of the input square wave sets off ringing instead of a settle. Splitting the poles with a Miller capacitor and a nulling resistor — 1.5 pF, after 2 pF proved too large to reach the required crossover — then reworking bias currents, overdrives and channel lengths backwards from the target loop gain, turns that into a settle to within 0.15% in 20 ns with 68.5° of margin, on 1.15 mW. One spec resists: the static error stays at 0.6% against a 0.2% target, because the simulated output resistances — and with them the DC loop gain — come in below the long-channel prediction, and closing that gap would cost bandwidth and area.
Uncompensated
Compensated
Try it — drag to add Miller compensation
Illustrative reconstruction from the reported phase-margin and settling figures above, not the original simulation waveform.
Lab 04
Tuning a band-gap reference flat to 0.09%
A low-voltage band-gap reference cancels the two temperature dependencies as currents rather than voltages: a PTAT current set by the thermal voltage across R1, a CTAT current set by the diode voltage across R2, and their sum mirrored into a third resistor. That indirection is what lets the output sit at 0.8 V instead of the ~1.2 V a classic band-gap is stuck with. The first hand-calculated sizing landed 7.6% high, at 860.7 mV, and still visibly sloped — traced back to the residual ~6 mV offset of the amplifier that balances the two branches, which pushes the PTAT current to 11.9 μA instead of the 10 μA the sizing assumed. Retuning the three resistors in order — R1 to put that current back (3.58 → 4.2 kΩ), R2 to null the slope at 27 °C, R3 to recentre the output — ends at 800.687 mV, 0.086% off the 0.8 V target, with the whole curve inside a 0.3 mV band from −40 °C to 85 °C.
